AHV85111 Datasheet

ABSOLUTE MAXIMUM RATING [1]

ESD RATINGS

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

RECOMMENDED OPERATING CONDITIONS: 

Valid at –40°C < T_J < 125°C, 10.8 V < V_DRV < 13.2 V, C_SEC(NET) = 47 nF, COUT = 1 nF, unless otherwise stated. [1][2]

[1] C_SEC(NET) is the net equivalent of C_SECP in series with C_SECN, i.e., (C_SECP × C_SECN) / (C_SECP + C_SECN).
[2] Not tested in production; guaranteed by design and bench characterization.
[3] Typical values should be chosen to match the ratio of VSECP to VSECN.
[4] Smaller C_SEC values than the recommended typical value can give higher voltage ripple on C_SEC.
[5] Larger C_SEC values will mean longer startup times.

Per JEDEC J-STD-033C, the AHV85111 devices are rated MSL3. This MSL3 rating means that once the sealed production packaging is opened, the devices must be reflowed within a “floor-life” of 168 hours (1 week) if they are stored in under standard ambient conditions (30°C and 60% relative humidity (RH)).

The peak reflow temperature should not exceed the maximum specified in MSL Rating table.

If the devices are exposed to the standard ambient for more than 168 hours, they must be baked before reflow to remove any excess moisture in the package and prevent damage during reflow soldering. The required bake times and temperatures are detailed in IPC/JEDEC standard J-STD-033C. If the devices are exposed to higher temperature and/or RH compared to the standard ambient of 30°C/60% RH, the floor-life will be shortened due to the increased rate of moisture absorption. If the actual ambient conditions exceed the standard ambient, it is recommended that parts should always be baked per IEC/JEDEC J-STD-033C before reflow as a precaution to avoid potential device damage during reflow soldering.

FUNCTIONAL BLOCK DIAGRAM

Figure 2: AHV85111 Block Diagram

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Package NH Pinout (Top View)

[1] Not cold tested in production (–40°C); guaranteed by design and bench characterization.

[2] Not tested in production; guaranteed by design and bench characterization.

[3] When VDRV is below the UVLO threshold, the driver output is actively held low.

[1] Not cold tested in production (–40°C); guaranteed by design and bench characterization.
[2] Not tested in production; guaranteed by design and bench characterization.

Typical IC Characteristics Curves

FUNCTIONAL DESCRIPTION

The AHV85111 is a self-powered isolated gate driver. Allegro’s patented Power-Thru technology allows the transfer of both PWM signal and gate power across a single transformer-based isolation barrier. This eliminates the need to provide an isolated bias supply to power the isolated side of the driver, greatly simplifying the sys- tem design. Only decoupling capacitors and programming resistors are required on the isolated side to generate the bipolar positive and negative gate drive rails V_SECP and V_SECN.

The AHV85111 driver has been optimized for driving the gate of typical Schottky-gate Enhancement-mode (E-mode) GaN FETs, such as those available from GaN Systems, Innoscience, ST, Nex- peria, GaN Power International, Taiwan Semiconductor, Rohm and others. An online FET selection tool can be downloaded from the Allegro website to assist system designers, to check compat- ibility of various FET devices with the driver.

The isolated V_SECP positive bias rail is locally regulated, using an external resistor divider connect to the FB pin. The balance of the secondary bias voltage becomes the unregulated negative rail V_SECN. The V_SECP rail regulates quite well versus PWM switching frequency f_SW at the IN pin, for a given fixed V_DRV level, and for a fixed load C_OUT at the OUTx drive pins—the load presented by the gate of the GaN FET being driven as long as the Q_G(TOT) versus frequency recommended operating area (ROA) curve recommendations are adhered to; see Figure 10 ROA curve. This is because the charge delivered per PWM cycle naturally increases in tandem with the charge consumed by the FET gate, so there is a good charge balance across a wide frequency range.

However, the V_SEC rails do vary with effective loading of the gate of FET being driven; as V_SEC levels fall, more charge is available to be delivered to the secondary side, while the charge consumed by the FET gate decreases with falling V_SEC levels. Therefore, the V_SEC rails will droop as far as needed until the charge delivered matches the charge consumed. For this reason, it is also very important to minimize the amount of charge diverted into any external loads. For example, a very low bias power external circuit can be powered using V_SEC, but the consumption should be minimal, to minimize the charge diverted away from the gate of FET. Similarly, if a gate-source pull-down resistor is desired on the load FET (to prevent false turn-on in the case of a manufacturing fault, such as an open-circuit gate turn-on resistor), the resistor value should be as large as possible. The recommended value is 100 kΩ, to minimize DC loading on V_SEC. Since DC load current converts to equivalent charge as Q = I × t, DC loading effects will become significantly more pronounced at lower PWM frequency, as the time duration t gets longer. In particular, it should be noted that the driver will attempt to regulate the positive rail V_SECP as priority, with the balance of charge diverted to create the negative rail V_SECN. In certain situations, such as low VDRV, high load FET Q_G, excessive external loading of V_SEC, high load FET gate leakage current IGSS, or a combination of these, there may be be insufficient charge available to create a sufficient or even any negative V_SECN. However, the ROA curve in Figure 10 indicates the supported operating range of Q_G versus PWM frequency that maintains a minimum V_SECN negative rail of –1 V or better.

Since there is just a single magnetic isolation barrier to transfer both PWM signal and gate power, this also greatly reduces the total parasitic capacitance between the primary-side and isolated side, to typically < 1 pF total for both signal and power channels. This is much less than the typical total parasitic capacitance value for a solution using a conventional isolated gate driver with a separate isolated DC-DC bias supply, where the capacitance contribution from the DC-DC isolation transformer could be as high as 10 pF or more. This reduction in isolation capacitance greatly reduces the level of noise injected back into the low-voltage control circuit by the high-voltage and high dv/dt switching nodes in the power stage half-bridge legs, reduces system level CommonMode (CM) EMI, and saves on power loss that occurs through repetitive charging and discharging of this parasitic capacitance between the high bus voltage level and ground.

APPLICATIONS INFORMATION

Bidirectional Enable/Disable EN Pin

EN is a bidirectional open-drain pin which requires an external resistor pull-up to the VDRV pin. The EN pin allows for management of startup and fault conditions between the PWM controller and multiple drivers, through use of a shared enable EN line. Either the PWM controller or the driver can pull the EN pin low via the EN bus, as shown in Figure 3. When the EN pin is pulled low (either externally or internally), this forces the driver into a mode where the IN pin signal is ignored, and the OUT pins are disabled and actively pulled low. When the EN pin goes high, normal driver operation is enabled.

In the event of an internal driver fault condition, such as UVLO or normal startup delay, the EN pin is actively pulled low internally by the driver. This driver pull-down can be detected by the PWM controller and used as a flag for an external fault, or to flag that the driver is ready, and PWM can commence.

The shared EN line is typically wired-AND with the controller EN pin, as shown in Figure 3. Multiple drivers can be connected in parallel with the controller on the shared EN line, such that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe startup of the system.

Figure 3: Example Wired-AND connection between driver and controller

Note that the EN pin has no internal pull-up or pull-down—the open-drain configuration relies on an external pull-up resistor for normal operation. Similarly, the EN pin must be actively pulled low externally to disable the driver. The EN pin should never be left floating or connected directly to VDRV or any other system bias voltage; a pull-up resistor must be used. The EN pin should be connected to VDRV through a pull-up resistor in a recommended range of 10 to 100 kΩ. The EN pin dv/dt when being pulled low or high should be at least 0.1 V/μs.

When the EN pin is pulled low, the driver output is disabled, and pulls down the OUTPD pin, regardless of the IN pin level (high or low). The driver goes to a low-power standby mode, and the isolated VSECP and VSEPN bias rails are allowed to discharge. The rate of decay of V_SECP and V_SECN depends on the value of the C_SECP and C_SECN capacitors.

When the EN pin is subsequently pulled high, the driver will re-enable, and the isolated VSEC bias rail will start to recharge. Even if the IN pin is connected to a PWM signal, the OUT pins will not respond until the VSECP rail exceeds the secondary UVLO threshold. The rate of rise of V_SECP depends on the PWM frequency at the IN pin. Worst-case slowest rise time is when IN = 0, using the slowest internal energy transfer mode. In this mode, the rise time will be approximately 250 μs for equivalent C_SEC of 47 nF to charge from zero to the rising UVLO threshold.

Startup and Shutdown Procedure

Any PWM signal applied to IN must remain low until V_DRV > UV threshold, to avoid parasitic charging of the V_DRV rail through the IN pin internal ESD structures. After V_DRV exceeds the UV rising threshold, a startup time delay t_START is required to allow all internal circuits to initialize and stabilize. During t_START, any IN signal inputs are ignored. EN internal pull-down will remain active during t_START, and will release (i.e., go open-drain) only when V_DRV has reached its UVLO voltage level, all on-chip voltages are stabilized, there is no overtemperature fault, and the internal t_START timer has elapsed. Thus, the EN pin can be used via a shared EN line to flag when t_START has elapsed, and the driver is ready to respond to PWM signals at the IN pin, as outlined above.

Typical startup waveforms are shown in Figure 4.

Figure 4: AHV85111 Startup Mechanism

Once V_DRV drops below UVLO falling threshold, the enable signal is pulled down and the driver output shuts down. The rate of decay of V_SEC is determined by the VSEC capacitance as shown in Figure 5.

Figure 5: Shutdown Mechanism

Refresh Pulse Mechanism

In cases when IN-PWM signal frequency is low or when IN is set to continuous 1 or 0, in order to prevent VSEC voltage decay, the AHV85111 implements an internal clock of 12 µs (t_REFRESH). When t_REFRESH elapses, the driver recharges VSEC rail to maintain output voltage. This condition persists until IN changes state as shown in Figure 6.

Figure 6: AHV85111 Refresh Mechanism

VSECP Voltage Setpoint

As shown in Figure 7, the feedback (FB) pin is used in conjunction with two resistors R_FB1 and R_FB2 to set the regulated output voltage between VSECP and SOURCE pins.

Figure 7: Rfb1 and Rfb2 used to set the desired 
VSECP-to-SOURCE positive bias rail regulation level

Decoupling capacitors CSECP and CSECN are connected from VSECP to SOURCE and VSECN to SOURCE respectively, to supply the peak gate charge and discharge currents. In addition, a capacitor CSECPN should be connected directly from VSECP to VSECN to ensure stability of the internal LDO—a value of 100 nF is recommended. A small noise filter cap is also recommended to be placed from FB to SOURCE to improve VSECP regulation robustness to noise. Typically 100 pF is recommended for R_FB2 = 100 kΩ

Table 1 shows resistance values (nearest E96 standard value) and associated outputs for an input voltage of V_DRV = 12 V, for typical V_SECP target setpoints. For other required V_SECP levels, Equation 1 can be used to calculate the required value for RFB1, assuming that the V_DRV level is high enough to allow V_SECP to regulate.

Table 1: V_SECP – V_SOURCE vs. Rfb1 value; Rfb2 = 100 kΩ, V_DRV = 12 V

The positive output voltage is regulated on-chip with respect to the SOURCE pin, at the level set by choice of R_FB2, assuming that the V_DRV level is sufficient to allow regulation at the target VSECP level. The remaining voltage overhead, unregulated, is the negative voltage drive (stored on CSECN).

Figure 8 shows curves of the typical positive output voltage range as a function of the input voltage V_DRV. Note that if the V_DRV level is too low to allow V_SECP to achieve regulation, V_SECN will be clamped to zero. Once the V_DRV level is sufficient to allow V_SECP to regulate, and excess secondary bias voltage will then appear on the negative rail V_SECN

Figure 8: Positive and negative output voltage vs. input VDRV

Effect of Temperature on V_SEC

At high operating ambient temperatures and low input PWM frequencies below 100 kHz, the total secondary-side bias rail, V_SECP – V_SECN, is reduced. Figure 9a shows that for minimum input supply voltage, V_DRV, and maximum recommended 6 V output set point, V_SECP, the total secondary-side bias voltage is not sufficient to maintain regulation of V_SECP and V_SECN is subsequently zero volts. Increasing V_DRV provides more secondary bias voltage and regulation is achieved.

At higher input frequencies, above 100 kHz, there is no reduction in V_SECP – V_SECN at maximum ambient temperature. Figure 9b shows there is sufficient secondary-side bias voltage to maintain regulation across the full input voltage range.

Figure 9: Effect of high ambient temperature 
on VSECP and VSECN

Operating Frequency and Thermal Derating

The maximum recommended PWM frequency is 1 MHz. However, the device internal dissipation, application PCB layout, and ambient temperature must also be taken into account to ensure that the internal recommended T_J(MAX) of 125°C is not exceeded.

Figure 10 shows the recommended operating area curve of Q_G(TOT) versus PWM frequency that will maintain a negative rail V_SECN of at least –1 V at nominal VDRV of 12 V. Operating further below this curve will result in even more negative off-state volt- age V_SECN. The AHV85111 can be operated above the curve of Figure 10, but the negative rail V_SECN will be limited, and in some cases can be close to zero.

Figure 10: Recommended Operating Area Curve Max QG(TOT) as a function of PWM Frequency fSW, VDRV = 12 V

The thermal derating curves of Figure 11 are based on the device thermal performance using JEDEC-standard PCB footprint and PCB design (layer count and size of copper planes for heatsinking). The actual thermal performance in the end system design should always be verified, since every system is different in terms of exact PCB design and ambient airflow from natural or forced convection

Because of the required creepage distance under the IC package to meet system safety requirements, it is not allowed to put a large copper plane under the IC for heatsinking purposes. Instead, it is recommended that the primary-side GND pins and secondary-side SOURCE pins be connected to appropriate ground planes on each side, and to maximize the size of these planes to maximize thermal performance. Multiple thermal vias to larger inner-layer ground planes can also help improve thermal performance.

The effective gate capacitance C_OUT that loads the OUTx drive pins can be estimated from the GaN FET datasheet. The FET total charge Q_G(TOT) is usually specified in nC, for a given V_GS voltage swing.

Knowing the value of C_OUT, the expected level of the second- ary supply rail V_SEC can be estimated from V_SEC vs. Frequency from Typical IC Characteristics curve. From C_OUT, V_SEC and the required PWM frequency F_SW, the total gate power can be calculated as follows:

Note that V_SEC in this case is the full V_GS voltage swing from posirtive to negative, i.e., V_GS = V_SECP – V_SECN. In practice, the system design will likely use external gate resistors to con- trol the FET turn-on and turn-off speed. The gate-drive power consumption P_GATE will be dissipated by the internal driver FET resistances and the external resistors, apportioned by the ratio of the resistances. The larger the value of the external resistors, the higher the power dissipation in those resistors, and the lower the dissipation in the internal driver resistances. To simplify the thermal estimates, and to add in design margin, it is assumed that all of the P_GATE power is dissipated inside the driver package.

The internal driver stage MOSFETs will consume drive power, and they will have switching losses, so there is an efficiency factor that needs to be accounted for when estimating the internal power consumed when delivering the P_GATE power.

Finally, the internal isolated bias power stage consumes power. As well as the IC quiescent power consumption, there are also drive, conduction and switching losses in the internal power FETs that drive and rectify the energy transfer through the internal isolation transformer, as well as the conduction and core losses of the transformer. These losses scale approximately linearly with PWM frequency.

Combining all of these loss mechanisms, the total package power dissipation (in mW) can be estimated using the following empirical formula, where f_SW is in kHz and P_GATE is in mW. This assumes a fixed V_DRV level of 12 V.

Using the standard JEDEC thermal impedances in the thermal characteristics table, the maximum allowed ambient temperature TA can be estimated from:

Alternatively, Figure 11 can be used to graphically estimate the allowable T_A(MAX) as a function of F_SW and C_OUT. The online FET selection tool can also be used to estimate expected driver temperature rise over ambient, and maximum allowed T_A.

Figure 11: AHV85111 thermal derating curve as a function of load capacitance COUT and PWM frequency fSW

WORKED EXAMPLE

What follows is an example calculation, based on the APE-K85110KNH-01-T-MH evaluation board. Assume the target switching frequency is 400 kHz, and the required maximum ambient temperature is 85°C.

The FET used on the board is a GS-66516-B from GaN Systems. From the GaN datasheet, the Q_G(TOT) is specified at 14.2 nC at 6 V V_GS swing. Therefore, the equivalent C_OUT is:

From figure 8, for this value of COUT the VSEC level can be estimated as approximately 7.5 V. Note that this evaluation board uses an external Zener circuit to limit the positive VGS swing to approximately 6.2 V, with the balance of the VSEC voltage appearing as a negative VGS in the off-state. Nevertheless, the full VGS swing must be used to estimate the gate power dissipation.

From this, the total package power dissipation can be estimated:

Now the maximum allowed ambient temperature can be verified to ensure that it meets the system requirement:

This equation shows that the design can meet the required maximum ambient temperature. However, as noted above, this uses R_TH(JA) estimates based on standardised JEDEC footprints and PCB layouts; the actual thermal performance must be verified in each individual application.

The maximum allowed ambient temperature can also be readily estimated from the curves in figure 7. Using FSW of 400 kHz, and C_OUT of approximately 2.4 nF, the estimate T_A(MAX) is approximately 96°C, which is close the calculated result using the empirical loss estimation.

V_DRV and C_SEC Design Guidelines

The output gate drive amplitude is always less than V_DRV due to internal impedances and voltage drops.

The total secondary-side bias rail, V_SECP – V_SECN, depends on the V_DRV level applied on the primary, and effective C_LOAD presented by the GaN FET being driven. C_LOAD = Q_G(TOT) / V_GATE, i.e., the total gate charge at a specified V_GATE, divided by V_GATE. C_ISS is not an equivalent measure of C_LOAD. C_ISS is a small signal equivalent capacitance, whereas C_LOAD is a large-signal equivalent.

The recommended value for C_SEC(NET) is approximately 10 to 20 times CLOAD (the equivalent gate capacitance), to give approximately 5% to 10% switching ripple on the VSEC rails. Other values are possible; however, lower values will result in higher ripple. Larger C_SEC(NET) value will require a longer startup time. The maximum recommended value of C_SEC(NET) = 100 nF should not be exceeded.

Typical Application Example 

Figure 12 shows a typical application for driving a GaN transistor with a bipolar drive arrangement.

Figure 12: APEK85111KNH-02-T-MH schematic for driving a GaN transistor with a bipolar drive arrangement

APEK85111KNH-02-T-MH is a design example for half bridge gate driver with GaN transistors. There is also a bipolar output drive 
configuration for additional protection against false turn-on events. The design parameters are shown in Table 2.

[1] Frequency depends on factors like heat sinking, temperature, high voltage decoupling capacitance and IN PWM duty cycle range

PBC LAYOUT

Layout Guidlines

The following are some key points to consider while doing the PCB layout for the best performance with AHV85111:

• Place the AHV85111 gate driver as close as possible to the transistor. This is necessary to minimize the path of the high peak currents. This arrangement will also minimize the loop inductance and noise injection on the gate signals.
• Ensure that the resistors connected between the isolated output drive pins to the gate of the transistor are high-power rated and have high power surge withstanding capability.
• Decoupling capacitors must be connected close to the VDRV/GND, REF/GND, VSECP/SOURCE, and VSECN/SOURCE pin-pairs.
• The path connecting to the source of the transistor should be minimized to avoid large parasitic inductances. The layout should have good thermal relief to help dissipate heat from the gate driver to the PCB. It is recommended to use vias to maximize thermal conductivity.

Further detailed PCB layout guidelines are available in the application note Design and Application Guide for the AHV85111.

Layout Example

SYSTEM IMMUNITY TO EXTERNAL TRANSIENTS

During various system-level events, large transient currents can flow for short periods. Examples of this include lightning surge testing to IEC61000-4-5, and system-level ESD testing to IEC61000-4-2. During these events, the large transient currents that flow can also create large stray magnetic fields, and these can also couple unintentionally to the isolated gate driver.

It is recommended to use the driver enable (EN) pin to achieve a power-train “safe-state” during such external transient events. An example of the use of this safe-state architecture is shown in Figure 14, for a Totem-Pole PFC power stage. When a surge event is detected, the system controller inhibits the PWM gate drive signal to both GaN and MOS legs, and also pulls down the open-drain Enable (EN) lines to all drivers. This puts the power train into a safe state and ensures a robust response to the surge event.

For further details, refer to the application note Design and Application Guide for the AHV85111

PACKAGE OUTLINE DRAWING